In the old days, "polling" was used instead of interrupts.  This is an older methodology where the CPU continually polls the devices, in a round-robin fashion - to see if they require attention.  However, polling wastes valuable CPU cycles.  Interrupts do not require the CPU to perform polling, since they actively send it a signal.  

There are two types of interrupts . . . hardware and software.  But whenever you hear people talking about interrupts, they are referring to the hardware interrupts.  Interrupts are often called IRQ's (Interrupt Requests).

Constantly, various devices need to be serviced by the CPU.  For example, you may have just hi a key on the keyboard, and the keyboard needs to have the CPU transfer the letter hit on the keyboard and display it on the screen.  If the CPU is busy with other duties it will have no idea that the keyboard needs to be serviced.   This is where the concept of an interrupt comes into play.  There are 15 hardware interrupts, numbered, conveniently, 1 to 15.  Upon bootup (startup of the PC), the devices are scanned, and if a new device is detected, it is assigned an interrupt (if one is available).  

When a device needs to be serviced by the CPU, it sends a signal to the CPU on it's interrupt line - which is one of the lines on the CPU frontside bus.  

The following shows what happens each time you move your mouse or click one of the buttons.  It sends an interrupt to the CPU (which in this case is busy running a User Program), the CPU stops running the program, services the mouse (i.e. looks to see how far and in what direction you moved the mouse), and then goes back to running the program.

NOTE:  this animation does not show the actual arrangement - where the mouse actually feeds into an interrupt controller, and single line runs to the CPU via the bus - more on that later.

PCs also support 256 types of software interrupts.   Interrupt signals initiated by programs are called software interrupts. A software interrupt is also called a trap or an exception. Each type of software interrupt is associated with an interrupt handler -- a routine that takes control when the interrupt occurs.  The complete list of interrupts and associated interrupt handlers is stored in a table called the interrupt vector table, which resides in the first 1 K of addressable memory. Click here for a list of All Intel Software Interrupts.

The 16 (actually, 15, since 2 is unavailable) Hardware Interrupts

Older PC's came with a single Interrupt controller that had eight different possible states (called "vectors" - which is just a hexadecimal value) - and therefore eight interrupts were available.  Even though there are 8 different interrupt vectors - only a single line, called "INT", is fed into the CPU.  An interrupt signal is received, when the INT line goes from high to low (positive voltage goes to no voltage), the CPU goes to an interrupt handling routine, which loads the vector into the CPU to tell it which Interrupt is requesting service (and correspondingly, which device).  Then the CPU services the device, and when finished, it continues doing what it was, prior to the interrupt.

Very quickly, 8 interrupts was not enough, and a second controller was added.  However, changing the CPU around would have taken a great deal of effort - so it was decided that the CPU would still only have the original 8 interrupt lines.  They "cascaded" the new 8 lines, by feeding them into Interrupt 2 on the old controller, and also piggy-backing them onto the original 8 lines.  This way, if #2 and one other interrupt line became active, the CPU would know that it belonged to the higher numbered set.  Interrupt 2 then became the "interrupt controller", or at least, that is what Windows calls it.  There are actually two controllers, with 8 lines apeice, and IRQ 2 is used as a special signaling line, which tips off the CPU whether the interrupt it is receiving is in the 0 to 7 range, or the 8 to 15 range.

On the original IBM XT computer, there were eight interrupts as follows, which are handled by a "Master Controller" :


Vector (in Hex)   




Timer tick (18.2 times/sec) 



Keyboard input 



Reserved for cascading interrupts 









Fixed disk controller 



Floppy disk controller 



Printer controller

Master Controller Interrupts

Very Soon Afterward, the IBM AT was developed, and added a second controller, which added eight more interrupts, which are handled by a "Slave Controller"  :


Vector (in Hex)   




Real-time clock 



Redirect cascade 









Auxiliary device 



Math coprocessor exception 



Fixed disk controller 




Slave Controller Interrupts (Cascaded onto IRQ2)

Since these interrupts are for the ancient XT and AT computers, the devices they are reserved for has changed dramatically over the years.  Here is a more typical, modern IRQ arrangement :


Cascaded Interrupts - as it turned out, in order to add a second INT line to the CPU - major, difficult revisions would have been required.  To get around that, the INT line of the second controller, the slave, is cascaded to the IRQ2 line of the first controller, the master. The eight interrupts (IRQ8 through IRQ15) from the second controller are mapped to interrupt vectors 112 (70h) through 119 (77h). Because these additional interrupts are effectively connected to the IRQ2 line of the master, they take priority over IRQ3 through IRQ7 of the master.

This renders IRQ2 useless for normal Interrupt operation, since it is being used by the slave, to signal the INT line on the CPU.  The slave has no INT line !!  However: for compatibility with the original PC, the Interrupt-line 2 is connected to the Line 9 on the 2nd controller.  (So, if a device on your PC is configured for Interrupt 2, it really uses Interrupt 9)

For example, suppose the hard drive issues an interrupt - the following would occur :

  1. the drive's interrrupt signal IRQ14, is cascaded onto IRQ2, and therefore IRQ2 is activated, and the INT line goes low, and signals the CPU
  2. the CPU sees that the INT line is low, and goes to load the vector value - which is an address of the interrupt routine
  3. since the hard drive has issued the interrupt request, it's vector value of 76h is loaded into the CPU.  The CPU only knows that something is requesting it's services.  It goes to s single register that contains the vector.  When a device issues an interrupt, it sends it's vector to that register
  4. the CPU, not know what device needs attention, loads the value in the register - 76h.  It then goes to the address, "76h", in ROM, and loads the interrupt handling routine for the Disk drive.  Finally, the CPU has exact instructions on what to do, and now knows it is servicing the disk drive.
  5. when the routine is completed, the hard drive has been services by the CPU, and the IRQ14 goes low - which vauses IRQ2 to go low

Sharing Interrupts - PCI cards have the ability to share interrupts, which has been a godsend to PC manufacturers and users.  After all these years, there are still only 15 interrupts.  For years, power users ran out of interrupts - until the advent of the interrupt sharing PCI architecture.  How does the CPU know which of several devices on a single interrupt, is requesting service?  Routines called "PCI Steering" are used to "steer" the CPU to the appropriate device, once an interrupt is issued.